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001: /*
002:  * include/linux/spi/spidev.h
003:  *
004:  * Copyright (C) 2006 SWAPP
005:  *      Andrea Paterniani <a.paterniani@swapp-eng.it>
006:  *
007:  * This program is free software; you can redistribute it and/or modify
008:  * it under the terms of the GNU General Public License as published by
009:  * the Free Software Foundation; either version 2 of the License, or
010:  * (at your option) any later version.
011:  *
012:  * This program is distributed in the hope that it will be useful,
013:  * but WITHOUT ANY WARRANTY; without even the implied warranty of
014:  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
015:  * GNU General Public License for more details.
016:  *
017:  * You should have received a copy of the GNU General Public License
018:  * along with this program; if not, write to the Free Software
019:  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
020:   */
021: 
022: #ifndef SPIDEV_H
023: #define SPIDEV_H
024: 
025: #include <linux/types.h>
026: 
027: /* User space versions of kernel symbols for SPI clocking modes,
028:  * matching <linux/spi/spi.h>
029:  */
030: 
031: #define SPI_CPHA                0x01
032: #define SPI_CPOL                0x02
033: 
034: #define SPI_MODE_0              (0|0)
035: #define SPI_MODE_1              (0|SPI_CPHA)
036: #define SPI_MODE_2              (SPI_CPOL|0)
037: #define SPI_MODE_3              (SPI_CPOL|SPI_CPHA)
038: 
039: #define SPI_CS_HIGH             0x04
040: #define SPI_LSB_FIRST           0x08
041: #define SPI_3WIRE               0x10
042: #define SPI_LOOP                0x20
043: #define SPI_NO_CS               0x40
044: #define SPI_READY               0x80
045: 
046: /*---------------------------------------------------------------------------*/
047: 
048: /* IOCTL commands */
049: 
050: #define SPI_IOC_MAGIC                   'k'
051: 
052: /**
053:  * struct spi_ioc_transfer - describes a single SPI transfer
054:  * @tx_buf: Holds pointer to userspace buffer with transmit data, or null.
055:  *      If no data is provided, zeroes are shifted out.
056:  * @rx_buf: Holds pointer to userspace buffer for receive data, or null.
057:  * @len: Length of tx and rx buffers, in bytes.
058:  * @speed_hz: Temporary override of the device's bitrate.
059:  * @bits_per_word: Temporary override of the device's wordsize.
060:  * @delay_usecs: If nonzero, how long to delay after the last bit transfer
061:  *      before optionally deselecting the device before the next transfer.
062:  * @cs_change: True to deselect device before starting the next transfer.
063:  *
064:  * This structure is mapped directly to the kernel spi_transfer structure;
065:  * the fields have the same meanings, except of course that the pointers
066:  * are in a different address space (and may be of different sizes in some
067:  * cases, such as 32-bit i386 userspace over a 64-bit x86_64 kernel).
068:  * Zero-initialize the structure, including currently unused fields, to
069:  * accommodate potential future updates.
070:  *
071:  * SPI_IOC_MESSAGE gives userspace the equivalent of kernel spi_sync().
072:  * Pass it an array of related transfers, they'll execute together.
073:  * Each transfer may be half duplex (either direction) or full duplex.
074:  *
075:  *      struct spi_ioc_transfer mesg[4];
076:  *      ...
077:  *      status = ioctl(fd, SPI_IOC_MESSAGE(4), mesg);
078:  *
079:  * So for example one transfer might send a nine bit command (right aligned
080:  * in a 16-bit word), the next could read a block of 8-bit data before
081:  * terminating that command by temporarily deselecting the chip; the next
082:  * could send a different nine bit command (re-selecting the chip), and the
083:  * last transfer might write some register values.
084:  */
085: struct spi_ioc_transfer {
086:         __u64           tx_buf;
087:         __u64           rx_buf;
088: 
089:         __u32           len;
090:         __u32           speed_hz;
091: 
092:         __u16           delay_usecs;
093:         __u8            bits_per_word;
094:         __u8            cs_change;
095:         __u32           pad;
096: 
097:         /* If the contents of 'struct spi_ioc_transfer' ever change
098:          * incompatibly, then the ioctl number (currently 0) must change;
099:          * ioctls with constant size fields get a bit more in the way of
100:          * error checking than ones (like this) where that field varies.
101:          *
102:          * NOTE: struct layout is the same in 64bit and 32bit userspace.
103:          */
104: };
105: 
106: /* not all platforms use <asm-generic/ioctl.h> or _IOC_TYPECHECK() ... */
107: #define SPI_MSGSIZE(N) \
108:         ((((N)*(sizeof (struct spi_ioc_transfer))) < (1 << _IOC_SIZEBITS)) \
109:                 ? ((N)*(sizeof (struct spi_ioc_transfer))) : 0)
110: #define SPI_IOC_MESSAGE(N) _IOW(SPI_IOC_MAGIC, 0, char[SPI_MSGSIZE(N)])
111: 
112: 
113: /* Read / Write of SPI mode (SPI_MODE_0..SPI_MODE_3) */
114: #define SPI_IOC_RD_MODE                 _IOR(SPI_IOC_MAGIC, 1, __u8)
115: #define SPI_IOC_WR_MODE                 _IOW(SPI_IOC_MAGIC, 1, __u8)
116: 
117: /* Read / Write SPI bit justification */
118: #define SPI_IOC_RD_LSB_FIRST            _IOR(SPI_IOC_MAGIC, 2, __u8)
119: #define SPI_IOC_WR_LSB_FIRST            _IOW(SPI_IOC_MAGIC, 2, __u8)
120: 
121: /* Read / Write SPI device word length (1..N) */
122: #define SPI_IOC_RD_BITS_PER_WORD        _IOR(SPI_IOC_MAGIC, 3, __u8)
123: #define SPI_IOC_WR_BITS_PER_WORD        _IOW(SPI_IOC_MAGIC, 3, __u8)
124: 
125: /* Read / Write SPI device default max speed hz */
126: #define SPI_IOC_RD_MAX_SPEED_HZ         _IOR(SPI_IOC_MAGIC, 4, __u32)
127: #define SPI_IOC_WR_MAX_SPEED_HZ         _IOW(SPI_IOC_MAGIC, 4, __u32)
128: 
129: 
130: 
131: #endif /* SPIDEV_H */
132: 

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